　　Today, the majority of electronic circuits (including microprocessors, microcontrollers,FPGAs, and CPLDs) are based on clocked logic, requiring a timing source. Depending on the frequency accuracy requirements, some employ oscillators while others use off-the-shelf quartz crystals in conjunction with the builtin oscillator circuit embedded in most microcontrollers and microprocessors.
　　Most if not all embedded solutions use the Pierce oscillator configuration,integrated as part of the SoC (systemon-chip). The obvious advantages include cost, size, and power compared to a standalone oscillator. The key limitation is the proper matching of the quartz crystal with the on-board Pierce oscillator.
　　Figure 1 outlines the oscillator block and the key components that influence the overall performance of the timing loop. Let the effective load capacitance, as seen by the crystal, be CL.
　　如今,大多数电子电路（包括微处理器,微控制器,FPGA和CPLD）都基于时钟逻辑,需要定时源. 根据频率精度要求,一些采用振荡器,而另一些采用现成的石英晶体与嵌入大多数微控制器和微处理器的内置振荡器电路相结合.
　　大多数（如果不是全部）嵌入式解决方案都使用皮尔斯振荡器配置,作为SoC（systemon-chip）的一部分集成. 与独立振荡器相比,明显的优势包括成本,尺寸和功耗. 关键的限制是石英晶振与板载皮尔斯振荡器的正确匹配.
图1概述了振荡器模块和影响定时环路整体性能的关键组件. 让晶体看到的有效负载电容为CL.

For example, let C1 = C2 = 27 pF; CIN = 5.0 pF and COUT = 10.0 pF and Board Strays = 0.50 pF.
例如,设C1 = C2 = 27 pF; CIN = 5.0pF,COUT = 10.0pF,板间距= 0.50pF.

　　Therefore specifying a crystal with 18.0 pF plating load capacitance would be the closest match for frequency accuracy. The selected capacitors primarily influence the overall oscillator loop capacitance, as seen by the crystal. This effective loop capacitance (CL from Eq. 1) determines how far the oscillator loop is resonating, relative to the desired resonant frequency. However, the overall longterm performance of the oscillator loop is influenced by the following factors:
　　因此,指定具有18.0 pF电镀负载电容的晶体将是频率精度最接近的匹配. 所选择的电容主要影响整个振荡器环路电容,如晶体所示. 该有效环路电容（来自等式1的CL）确定振荡器环路相对于所需谐振频率谐振的程度. 但是,振荡器环路的整体长期性能受以下因素影响：
• The reactive impedance (Xc) of these loop capacitors.
• The inverter amplifier’s transconductance (gm).
• The presence or absence of the current limiting resistor (Rs).
• The presence or absence of the automatic gain control (AGC) or automatic level control (ALC); with-in the integrated oscillator circuit.
These factors collectively set the boundary condition of the design. This boundary condition, commonly referred to as the safety factor (SF), is an important parameter to ensure that the product design has sufficient margin to accommodate part-to-part and lot-to-lot variations; as well as, eliminating product performance uncertainty in production volume. Historically, design engineers have optimized their circuit performance via trial and error, at the expense of sig.
•这些环路电容器的无功阻抗（Xc）.
•逆变器放大器的跨导（gm）.
•是否存在限流电阻（Rs）.
•是否存在自动增益控制（AGC）或自动电平控制（ALC）; 与集成振荡器电路配合使用.
这些因素共同设定了设计的边界条件. 这种边界条件,通常称为安全系数（SF）,是确保产品设计具有足够的余量以适应零件到零件和批次间差异的重要参数; 以及消除产品性能不确定性的产量. 从历史上看,设计工程师通过试验和错误优化了电路性能,但牺牲了信号.
Fig. 1: The oscillator block and the key components that influence the overall performance of the timing loop.

图1：振荡器模块和影响定时环路整体性能的关键部件.
　　nificant investment in time. Further, to properly determine the oscillator loop dynamics, the most accurate determination is made by breaking the oscillator loop and conducting key measurements using specialized equipment such as a current probe.
　　及时投入.此外,为了正确地确定振荡器环路动态,通过使用诸如电流探头的专用设备断开振荡器环路并进行关键测量来进行最准确的确定.
　　Lastly, these measurements become increasingly sensitive if the timing loop is driven by a tuning-fork (32.768- kHz) crystal. These crystals are extremely sensitive to loading effects and to accurately determine the in-circuit behavior of these components, extreme care and accuracy is essential. For instance, Automotive, medical and consumer electronics solutions typically use tuning fork crystals for their real-time-clocking (RTC) needs. If the selected SOP has limited gain margin, there is a high probability that some percentage of these crystals will not properly start under adverse conditions, such as cold operating temperature (–40°C).
　　最后,如果定时环由音叉（32.768-kHz）晶体驱动,则这些测量变得越来越敏感.这些晶体对负载效应非常敏感,并且准确地确定这些元件的在线行为,极其谨慎和准确性至关重要.例如,汽车,医疗和消费电子解决方案通常使用音叉晶体来满足其实时时钟（RTC）需求.如果所选择的SOP具有有限的增益裕度,则很可能这些晶体中的某些百分比在不利条件下（例如冷工作温度（-40℃））不能正常启动.
Another example would be a product designed to address the ZigBee related solutions, which typically has a hard boundary condition of ±40 ppm relative to the carrier, for proper operation. This ±40-ppm operational window actually needs to account for
　　另一个例子是设计用于解决ZigBee相关解决方案的产品,该解决方案通常具有相对于载波±40ppm的硬边界条件,以实现正确操作.这个±40 ppm的操作窗口实际上需要考虑
• Quartz crystal set tolerance.
• Shift through reflow.
• Stability over temperature.
• Aging during product-life-cycle (such as 5 years).
• Frequency pushing and pulling.
If the oscillator loop is not optimized, most of the ±40 ppm can be potentially consumed by the set tolerance of the quartz crystal alone, thereby causing potential field failures.
•石英晶体设置公差.
•通过回流转换.
•温度稳定性.
•产品生命周期中的老化（例如5年）.
•频率推拉.
如果振荡器环路未经优化,则单独使用石英晶体的设定公差可能会消耗大部分±40 ppm,从而导致潜在的现场故障.
　　These frequency domain failures could be primarily attributed to the oscillator frequency drifting over temperature or long-term aging, to the point that the oscillator loop is no longer within the allocated ±40-ppm operational window. Besides the issues related to oscillator-loop accuracy in the frequency domain, the oscillator-loop drive level must also be properly quantified to ensure acceptable product performance over temperature and time. For instance, a typical 24-MHz SMT quartz crystal has a drive level specification of 100 µW max. If the quartz crystal is consistently being driven at some multiple of this limit, such as 200 µW; it is possible that, over temperature or time, the oscillator circuit might start to resonate permanently or intermittently — at a spurious or overtone mode of the quartz crystal. Although relatively low on the checklist of design engineers, the Pierce oscillator driven by an external resonator — such as a quartz crystal — can present a significant challenge during a typical product launch. Characterizing the oscillator loop during the design phase should be a priority to mitigate the risk during product launch as well as field returns down the road.
　　这些频域故障主要归因于振荡器频率随温度漂移或长期老化,导致振荡器环路不再在分配的±40 ppm操作窗口内.除了与频域振荡器环路精度相关的问题外,还必须对振荡器环路驱动电平进行适当量化,以确保在整个温度和时间内可接受的产品性能.例如,典型的24 MHz SMT石英晶体的驱动电平规格最大为100μW.如果石英晶体始终以该极限的某个倍数驱动,例如200μW;在温度或时间上,振荡器电路可能会开始永久或间歇地谐振 - 处于石英晶体的寄生或泛音模式.虽然设计工程师的清单相对较低,但是由外部谐振器（例如石英晶体）驱动的皮尔斯振荡器在典型的产品发布期间可能是一个重大挑战.在设计阶段表征振荡器回路应该是减少产品发布期间风险以及现场返回的优先事项.
　　The Pierce Analyzer System To overcome these challenges and provide an accurate assessment of the oscillator loop dynamics, Abracon’s Advanced Engineering Team has developed a proprietary Pierce Analyzer System (PAS), designed to analyze both the standalone crystal, as well as the performance of that particular crystal in the final circuit.
Key PAS features
• Circuit characterization; provides best possible match between Quartz Crystal, oscillator loop and associated components.
• Eliminates probability of oscillator startup issues related to inadequate design or marginal component performance.
• Eliminates production launch issues related to crystal oscillator based timing circuit.
• Solves for design margin uncertainty.
• Provides customer’s oscillator circuit overview in the form of a detailed report, which could be an ideal 3rd party assessment for the design 　　history file or PPAP documentation. This report encompasses both the stand-alone crystal performance, as well as in-circuit behavior outlining safety factor as a function of crystal’s ESR, etc.
　　皮尔斯分析仪系统为了克服这些挑战并提供振荡器回路动态的准确评估,Abracon的高级工程团队开发了专有的皮尔斯分析仪系统（PAS）,旨在分析独立晶体以及特定晶体的性能晶体在最后的电路中.
关键PAS功能
•电路特性;提供石英晶体,振荡器环路和相关组件之间的最佳匹配.
•消除与设计不足或边缘组件性能相关的振荡器启动问题的可能性.
•消除与基于晶体振荡器的定时电路相关的生产启动问题.
•解决设计边际不确定性问题.
•以详细报告的形式提供客户的振荡器电路概述,这可能是设计历史文件或PPAP文档的理想第三方评估.本报告既包括独立的晶体性能,也包括作为晶体ESR等函数的安全系数的在线行为.

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